The breath-taking increase in performance of nanoelectronic circuits has been continuously supported by the uninterruptedminiaturization of devices and interconnects. Among the most crucial technological changes lately adopted by thesemiconductor industry is the introduction of a new type of multi-gate three-dimensional (3D) transistors . This technologycombined with strain techniques and high-k dielectrics/metal gates offers great performance and power saving advantages overthe planar structures and allows continuing scaling down to 14nm feature size and beyond. In order to continue with scalingfurther, a new material with improved transport characteristics for the channel must be introduced . Although single deviceswith gate length as short as a few nanometers have been demonstrated , fabrication, control, and integration costs combinedwith reliability issues will gradually bring conventional transistor scaling to an end. The principle of transistor operation isfundamentally based on the charge of an electron interacting with the gate voltage induced electrostatic field. Another intrinsicelectron characteristic, the electron spin, attracts at present much attention as a possible candidate for complementing or evenreplacing the charge degree of freedom in future electronic devices. The electron spin state is characterized by two projections onan axis and could be potentially used in digital information processing. In addition, it takes an amazingly small amount of energyto invert the spin orientation. The key advantages of all spin-based computing as compared to a conventional processor withequivalent functions are zero static power, small device count, and low supply voltage, as listed in a recent review .Silicon, the most important material of electronics, predominantly consists of nonmagnetic 28Si nuclei and is characterized byweak spin-orbit interaction. Because of these properties the electron spin lifetime in silicon is relatively long. This makes silicon aperfect candidate for spin-driven device applications. However, even a demonstration of basic elements necessary for spin-relatedapplications, such as spin injection, detection, and propagation was missing until recently. The fundamental reason has beenidentified as an impedance mismatch problem . Even though there is a large spin imbalance between the majority and minorityspins in a metal ferromagnet, both channels with spin-up and spin-down are equally populated in a semiconductor due to thesmall density of states as compared to that for the minority spins in a ferromagnet. In other words, because of the large resistanceof the semiconductor, the voltage applied to the contact between the ferromagnet and the semiconductor drops completelywithin the semiconductor, and the properties of the contact are dominated by the non-magnetic semiconductor, thus resultingin a current without spin polarization. A solution to overcome this problem is to use the hot electron injection ; however, theefficiency of spin injection and detection is low. Another solution to the impedance mismatch problem is the introduction of apotential barrier between a metal ferromagnet and a semiconductor . In this case the influx of carriers from the ferromagnetinto the semiconductor is reduced proportionally to the ration of the densities of states in a semiconductor and a ferromagnet. Thisguarantees the spin injection into the semiconductor. A successful experimental proof of spin injection at low temperature from aniron electrode through aluminium oxide  was demonstrated in 2007. At room temperature spin injection into n- and p-dopedsilicon was shown in 2009 . The authors used heavily doped silicon samples to avoid an extended depletion layer causing largetunnel barriers. The problem of making good contacts with low resistance per area is critical for spin injection. Tunnel contactsmade of a single layer graphene  have been shown to be close to optimal . Electrical spin injection through silicon dioxideat temperatures as high as 500K has also been demonstrated .Regardless of an ultimate success in demonstrating spin injection into silicon at room temperature, there are unsolved issues,which may compromise the present understanding of the spin injection process in general. One problem is a several orders ofmagnitude discrepancy between the signal measured in a scheme where the same ferromagnetic contact is used to inject and tomeasure the spin accumulation and its theoretical value . Similar observations were also made for germanium  as well asfor other semiconductors . These discrepancies are heavily debated , ,  and more research is needed to resolvethe controversies. The excess spin is not a conserved quantity: While diffusing, it gradually relaxes to its equilibrium value which is zero in a nonmagnetic semiconductor. Spin can propagate 350 microns through a silicon wafer at 77K . The spin diffusionlength in silicon at room temperature is around 200nm . In a confined electron structure the spin lifetime is further reduceddue to the additional spin relaxation at the interfaces . This shortens the spin diffusion length further, which represents a threatfor using CMOS transistors for spin-driven applications.Technologies to boost the spin lifetime are needed. The spin lifetime is determined by the spin-flip processes. Several importantspin relaxation mechanisms are identified [19, 20]. The Elliot-Yafet mechanism is mediated by electron-phonon interaction andthe intrinsic interaction between the orbital motion of an electron and its spin is responsible for the spin relaxation in silicon.The main contribution to the spin relaxation is due to optical phonon scattering between the valleys residing at differentcrystallographic axis, or f-phonon scattering . Stress lifts the degeneracy between the non-equivalent valleys and can suppressthe spin relaxation by a factor of three. The theory of spin relaxation in inversion layers and thin films must account for the mostrelevant scattering mechanisms, namely electron-phonon interaction and surface roughness scattering. It turns out that in (001)silicon films, where the non-equivalent valley degeneracy is lifted by confinement, the spin lifetime is controlled by the intervalleyscattering processes between the equivalent valleys . This is in contrast to the effect on the momentum relaxation time whichis determined by the elastic intravalley scattering. Uniaxial stress along  direction lifts the remaining degeneracy between thetwo equivalent valleys thus reducing the intervalley spin relaxation . This results in a giant, close to two orders of magnitude,spin lifetime enhancement  at saturation for shear strain values of about 1.5%. At the intermediate strain values the spinlifetime increase is almost exponential. Strain techniques are now routinely used to boost the electron mobility. It is thereforestraightforward to apply the same techniques to obtain a spin lifetime close to 1ns required for spin-driven applications in CMOStransistor technology.For building a SpinFET  purely electrical spin manipulation in the channel is required. However, the channel lengthrequired to rotate the spin substantially in silicon is several microns and thus too large . The only viable option left to usenanoscale CMOS is likely to convert a MOSFET to a SpinFET by adding the spin degree through introducing ferromagnetic sourceand drain contacts . The current in this structure depends on the relative orientation of the magnetizations of source anddrain paving the path towards programmable nonvolatile logic. The contact magnetization direction can be switched electricallyby using spin torque transfer. However, due to the low spin injection efficiency at room temperature, a SpinFET has not yet beenrealized. Although significant progress in understanding spin injection, transport, and detection in silicon has been achieved,more research is urgently needed to increase the spin injection efficiency at room temperature and to resolve the issue of spinmanipulation by pure electrical means. The most viable option for practical spin-driven applications in the near future is to usemagnetic tunnel junctions (MTJs). MTJ-based spin transfer torque MRAM is CMOS compatible, non-volatile, and scalable. Itis fast and, in addition, characterized by an infinite endurance and high density. 64Mb MRAM arrays are already in production.A combination of an MTJ with a MOSFET opens a new opportunity to built non-conventional non-volatile logic-in-memorysystems .